Challenges in Cell-Based Design of Very-High-Speed Si-Bipolar IC's at 100 Gb/s Print
Sunday, 30 September 2007 13:00

[IEEE BIPOLAR/BiCMOS CIRCUITS AND TECHNOLOGY MEETING 2007]

Challenges in Cell-Based Design of Very-High-Speed Si-Bipolar IC's at 100 Gb/s

M. Möller,1,2

1 MICRAM Microelectronic GmbH, Bochum, Germany
2 Saarland University, Department of Electronics and Circuits, Germany

Abstract:

A cell-based design concept for higher integrated SiGe-bipolar circuits at 100 Gb/s is presented and discussed with regard to performance limitations. The results of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with onchip clock- and data-recovery.

 

Full article was published at 2007 IEEE BIPOLAR/BiCMOS CIRCUITS AND TECHNOLOGY MEETING Boston, Massachusetts, OCTOBER 1 – 2, 2007